1. Field of the Invention
The present invention relates generally to high density integrated circuit devices, and more particularly to interconnect structures for multi-level three-dimensional stacked devices.
2. Description of Related Art
In the manufacturing of high density memory devices, the amount of data per unit area on an integrated circuit can be a critical factor. Thus, as the critical dimensions of the memory devices approach lithographic technology limits, techniques for stacking multiple levels of memory cells have been proposed in order to achieve greater storage density and lower costs per bit.
For example, thin film transistor techniques are applied to charge trapping memory in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory”, IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node”, IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
Also, cross-point array techniques have been applied for anti-fuse memory in Johnson et al., “512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells” IEEE J. of Solid-State Circuits, vol. 38, no. 11, November 2003. See, also U.S. Pat. No. 7,081,377 to Cleeves entitled “Three-Dimensional Memory”.
Another structure that provides vertical NAND cells in a charge trapping memory technology is described in “Novel 3-D Structure for Ultra-High Density Flash Memory with VRAT and PIPE” by Kim et al., 2008 Symposium on VLSI Technology Digest of Technical Papers”; 17-19 Jun. 2008; pages 122-123.
In three-dimensional stacked memory devices, conductive interconnects used to couple the lower levels of memory cells to decoding circuitry and the like pass through the upper levels. The footprint or plan view area of these interconnects can significantly reduce the amount of area available for memory cells in the upper levels. Also, the cost to implement the interconnections increases with the number of lithographic steps needed. One approach to reduce the number of lithographic steps is described in Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 Jun. 2007; pages 14-15.
However, in the structure described in Tanaka et al., the size of each succeeding level in the stack is smaller than the lower levels. This results in significantly smaller memory areas in the upper levels, reducing the memory density and increasing the cost per bit. Also, there is a practical limit to the number of levels that can be layered in this way. Thus, although the benefits of higher density are achieved using three-dimensional stacked memory, the reduced memory density and resulting higher per bit manufacturing costs for the upper layers limit the use of the technology.
It is therefore desirable to provide three-dimensional 3D stacked devices with an interconnect structure for the multiple levels having a very small footprint, as well as methods for manufacturing such devices that can be carried out at lower costs.